Field of the Disclosure
The present disclosure relates generally to a flip-flop, and more particularly, to a high-speed domino-based flip-flop.
Description of the Related Art
A high speed flip-flop with minimized area and reduced power is desirable in many applications such as a mobile terminal.
The difference between a time at which a clock signal (CK) of a flip-flop controls an output (e.g. Q) of the flip-flop to transition to a predetermined output logic level and a time (tckq) at which the output of the flip-flop actually transitions to the predetermined logic level, which is commonly referred to as a CK to Q delay, is a factor that determines the maximum operating frequency (e.g. the minimum time period of a clock cycle (Tck)) of the flip-flop. Setup time (tsetup) (i.e., a time for which inputs to a flip-flop must be present and stable before a clock signal commands an output of the flip-flop to transition to a predetermined logic level) is also a factor in determining the maximum operating frequency of a flip-flop. A propagation delay (tpd) for any combinatorial logic that is used with a flip-flop is also a factor in determining the maximum frequency of operation of a flip-flop. The sum of these three factors determines the minimum clock cycle of a flip-flop, as indicated in Equation (1) as follows:Tck≥tckq+tpd+tsetup  (1)
Absent clock skew, only tckq and tsetup are a function of the design of a flip-flop. Thus, reducing tckq and tsetup of a flip-flop will increase its operating frequency (i.e., reduce its Tck).
A conventional domino-based set-reset (SR) flip-flop, which includes a master latch and a slave latch, uses a clock signal (CK) of the flip-flop to pre-charge and evaluate the logic level of the master latch. That is, a conventional domino-based flip-flop pre-charges nodes of the master latch and the slave latch when CK is low and evaluates them when CK is high. The conventional domino-based flip-flop also includes footers, which are used to discharge a pre-charged node during the evaluation cycle, if the inputs indicate that the nodes should be low. If the inputs indicate that a pre-charged node should remain high then the node is not discharged during the evaluation cycle.
The setup time of a domino-based SR flip-flop is reduced as compared to an SR flip-flop that does not use domino logic (e.g. an SR flip-flop that uses all static logic). However, a domino-based SR flip-flop executes a pre-charge cycle and an evaluation cycle during each clock cycle whether or not the nodes in the SR flip-flop being evaluated are required to change due to the values of the inputs to the SR flip-flop. Thus, a domino-based flip-flop consumes power when it is not necessary to do so.
An SR flip-flop uses a complimentary data signal (data) to re-set the SR flip-flop, which requires an evaluation of the complimentary data signal. It takes time to generate a compliment of a signal (e.g. a propagation time of an inverter to generate a compliment of a signal input to the inverter). In addition, power is consumed in generating and evaluating the complimentary signal. The consequence of which is a longer evaluation time, which increases the CK to Q delay, and higher power consumption.
Thus, there is a need for a flip-flop that has a lower CK to Q delay, a lower setup time, and consumes less power.